Dynamic Random Access Memory (DRAM) circuits are typically used in semiconductor data processing systems to provide inexpensive memory for use during a myriad of data processing operations. Current data processing systems which have implemented multiple data processors that access common DRAM circuits typically require an external multiplexer for providing proper address multiplexing. Such address multiplexing is required to provide a proper address to the DRAM circuit during a memory access operation. Because the pin count of a DRAM circuit is typically limited, a multiplexer is required to provide either a row address or a column address to a same preselected portion of integrated circuit pins of the DRAM circuit when the appropriate control is provided by one of the multiple data processors. The data processor provides a RAS (Row Address Strobe) or a CAS (Column Address Strobe) signal to the DRAM circuit to indicate whether a row address or a column address is currently being provided on the preselected portion of integrated circuit pins of the DRAM circuit. Additionally, a DRAMW signal is provided to indicate a read or a write access to the DRAM circuit. Note, in a typical DRAM circuit, the RAS signal indicates the preselected portion of integrated circuit pins of the DRAM circuit are receiving a row address value and the CAS bus indicates the preselected portion of integrated circuit pins of the DRAM circuit are receiving a column address. In addition to the RAS, CAS, and DRAMW signals, the data processor must also generally designate at least one integrated pin to provide control for the multiplexer. In an art area in which the number of integrated circuit pins is limited, the use of a single pin for providing multiplexer control may be onerous to designers of the data processing system.
Furthermore, the external logic required to implement the multiplexer in prior art implementations often adds a substantial amount of overhead cost to the data processing system which include an external master. In data processing systems using the AM29200 manufactured by Advanced Micro Devices, and the PPC403GA manufactured by International Business Machines, external multiplexing such as that described above is required. Each of these systems requires a configuration such as that illustrated in FIG. 1. Therefore, although current implementations of DRAM controllers function adequately, a need exists for a data processing system which does not require the use of the aforementioned multiplexer or an additional external integrated circuit pin to control that multiplexer.
Another area which causes concern for data processing system designers results when an internal and external master device both use chip select and write enable generation logic in a data processor. When an external master initiates a bus transfer using internal chip select generation, often times, the external master requires a different amount of time to access the chip selected memory than an internal master. This is because the external master address and bus attributes are not available to the internal controller in the same amount of time as the internal master address and bus attributes. If this is the case and the external master wants to use the internal chip select generation logic, the prior art solutions may either require the internal master access to be changed to match the external master access or may allow the internal master access to be one clock cycle shorter than the external master access.
If a user can not use either of the above solutions, the user will be unable to use the internal chip select and write enable generation logic. In this situation, the user must add such logic to the external system for external master accesses. Therefore, a need also exists for a data processor which will allow a user to take advantage of internally implemented chip select and write enable generation logic when an external master has accessed an external memory, without requiring the timing of the external master access to be the same or one cycle slower than that of an internal master access.